Computing memory systems are generally composed of one or more dynamic random access memory (DRAM) integrated circuits, referred to herein as DRAM devices, which are connected to one or more processors. Multiple DRAM devices may be arranged on a memory module, such as a dual in-line memory module (DIMM). A DIMM includes a series of DRAM devices mounted on a printed circuit board (PCB) and are typically designed for use in personal computers, workstations, servers, or the like. There are several different types of memory modules, including: unbuffered DIMMs (UDIMMs) where both the command/address and data busses attach directly to the DRAM components; registered DIMMs (RDIMMs) where the command/address bus is buffered but not the data bus; and load-reduced DIMMs (LRDIMMs) in which there are buffer chips for both the command/address bus as well as the data bus. In general and due to the difficult electrical signaling nature of the memory channel, the higher the capacity and bandwidth requirements of a memory channel, the more buffering is required to achieve desired performance.
Successive generations of DRAM components have appeared in the marketplace with steadily shrinking lithographic feature size. As a result, the device storage capacity of each generation has increased. Each generation has seen the signaling rate of interfaces increase, as well, as transistor performance has improved.
Unfortunately, one metric of memory system design which has not shown comparable improvement is the maximum number of modules that a single memory channel can support. This maximum number of modules has steadily decreased as the signaling rates have increased.
The primary reason for this decrease is the link topology used in standard memory systems. When more modules are added to the system, the signaling integrity is degraded, and high-speed signaling becomes more and more difficult. Typical memory systems today are limited to just one or two modules when operating at the maximum signaling rate.
Some future memory systems may be limited to a single rank of devices (or a single rank of device stacks) on a single module at the highest signaling rates.